The present invention relates to digital microprocessors, and more particularly to monitoring the operation and performance of digital microprocessors.
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Prefetching of instructions into an internal buffer helps to maintain instruction throughput. A cache internal to the microprocessor may provide shorter instruction access times.
Known microprocessor debugging environments provide code profiling capability which allows the amount of cycles or instructions required to execute a specified routine or piece of code to be determined. Breakpoint monitoring is a known technique in which instruction code execution is interrupted when a preselected instruction is executed or when data is read or written from/to selected addresses.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as disk controllers for portable computers and mobile telecommunications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
A method and apparatus has now been discovered for providing chained breakpoint operation in a microprocessor with independent, or decoupled, fetch units. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims.
In accordance with a first aspect of the invention, there is provided a microprocessor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer along with respective mark tags and chain tags from the tag circuitry. The instruction execution pipeline has a point of no return instruction pipeline stage. Breakpoint state machine circuitry is connected to the point of no return instruction pipeline stage and is operable to monitor mark tags and chain tags received by the point of no return instruction pipeline stage. The breakpoint state machine is further operable to indicate a chained breakpoint event when a chain tag is received after a mark tag from the point of no return instruction pipeline stage.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A microprocessor is operable to execute a sequence of instructions. A mark event or a chain event is generated when instructions in the sequence of instructions are prefetched into an instruction buffer and stored as tags in the instruction buffer with an associated instruction. Each instruction in the sequence of instructions is transferred from the instruction buffer to an instruction execution pipeline connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags, wherein the instruction execution pipeline has a point of no return instruction pipeline stage. The mark tags and chain tags received by the point of no return instruction pipeline stage are monitored and a chained breakpoint event is indicated when a chain tag is received after a mark tag.